• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an active region and a method for forming a device isolation layer of a semiconductor device suitable for improving the isolation characteristics of a device by continuously depositing an APCVD oxide layer and an HDPCVD oxide layer in an STI process to fill a trench. Forming a thermal oxide layer on the surface of the semiconductor substrate including the device isolation region for isolating the semiconductor layer, and forming a nitride layer on the thermal oxide layer, and selectively etching the nitride layer to remove the device isolation region. Forming a trench of a predetermined depth by selectively etching the thermal oxide layer and the semiconductor substrate using the mask as a mask, and forming a trench having a predetermined depth, and forming the thermal oxide layer again on the trench surface and forming the thermal oxide layer and the patterned nitride layer Forming an APCVD oxide layer on the entire surface including the entire surface of the APCVD oxide layer;面) the step of forming and heat treatment of the oxide film layer and the HDPCVD, made by the grinding of the HDPCVD oxide film layer in a CMP process comprising a step of leave only the trench portion.
    公开号:KR19990038702A
    申请号:KR1019970058531
    申请日:1997-11-06
    公开日:1999-06-05
    发明作者:박진원
    申请人:구본준；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Device isolation layer formation method of a semiconductor device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a device isolation layer of a semiconductor device suitable for improving isolation characteristics of a device by continuously depositing an APCVD oxide layer and an HDPCVD oxide layer in an STI process to fill a trench. will be.
    In general, a process of forming a device isolation region for isolating cells and cells has emerged as an important technology in the miniaturization technology of semiconductor devices, and research on them is being actively conducted.
    In large-capacity memories, the width of the device isolation region is a major factor in determining the size of the entire memory device.
    In general, it is a selective oxidation method (Local Oxidation of Silicon) used as a device isolation region forming technology. The selective oxidation method described above is characterized in its process, and a phenomenon called buzz big occurs, which may lower the reliability of the device. For this reason, researches to improve the selective oxidation method have been conducted. Typical examples are Side WAll Masked Isolation (SWAMI) and Selective Polysilicon Oxidation (SEPOX). Another method being proposed is to form grooves in the substrate and to insulate the substrate, and representatively, shallow trench isolation (STI).
    In the STI method, a trench is formed in a substrate and an insulating material is buried to form an isolation layer. In the initial stage, the trench is buried using a USG (Undoped Silicate Glass) film by plasma oxide film or APCVD (Atmospheric Pressure Chemical Vapor Deposition). It was.
    However, as the pattern dimension of the device is further reduced, a method of filling a trench using an HDPCVD (High Density Plasma Chemical Vapor Deposition) oxide film has been proposed.
    Hereinafter, a device isolation layer of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
    1A and 1B are process cross-sectional views of a device isolation layer of the prior art, and FIGS. 2A and 2B are process cross-sectional views of another device isolation layer of the prior art.
    1A and 1B illustrate a method of filling a trench using an HDPCVD oxide film, and the process sequence is as follows.
    First, as shown in FIG. 1A, the nitride film layer 3 is formed on the initial oxide film of the semiconductor substrate 1 and selectively etched. The thermally oxidized film layer 2 is formed by performing a thermal oxidation process using the patterned nitride film layer 3 as a mask.
    Subsequently, the semiconductor substrate 1 is selectively etched by selectively etching the nitride film layer 3 in a portion where the thermal oxide layer 2 is not used as a device isolation layer (a portion where a relatively narrow width of the device isolation layer should be formed). Etch a depth to form a trench.
    The plasma oxide layer 4 is formed on the entire surface including the thermal oxide layer 2 and the trench.
    Subsequently, the USG layer 5 is formed on the plasma oxide layer 4 by the APCVD process. At this time, the trench region is completely filled by the USG layer (5).
    As shown in FIG. 1B, the device isolation layer is formed by etching back the USG layer 5 and the plasma oxide layer 4 by the APCVD process so as to remain only in the trench region.
    As described above, the device isolation layer forming method using the plasma oxide layer 4 and the USG layer 5 by the APCVD process is difficult to apply to mass production while the design rules of the semiconductor device are reduced, and thus the device isolation layer using the oxide film by the HDPCVD process is difficult. The formation method is used.
    In the method of forming a device isolation layer using an oxide film by an HDPCVD process, first, as shown in FIG. 2A, a thermal oxide film 2 is formed on a semiconductor substrate 1 and a nitride film layer 3 is formed on the thermal oxide film 2. To form.
    The nitride layer 3 is selectively etched so as to remain only in portions except the device isolation region. The trench is formed by etching the exposed thermal oxide layer 2 and the semiconductor substrate 1 to a predetermined depth using the patterned nitride layer 3 as a mask.
    Subsequently, the thermal oxide layer is formed again on the trench surface and the HDPCVD oxide layer 6 is formed on the entire surface including the trench.
    As shown in FIG. 2B, the device isolation layer is formed by etching back the HDPCVD oxide layer 6 so as to remain only in the trench portion.
    Such a device isolation layer forming process of the prior art has the following problems.
    First, in the case of filling the trench using the APCVD oxide film, due to the material characteristics of the APCVD oxide film, voids occur in the narrow portion of the device isolation layer, resulting in deterioration of the device isolation property and the width of the device isolation layer. In large areas, the center is dished deep dishing, which requires additional processing to compensate for the defect.
    In the case of filling the trench using the HDPCVD oxide film used to solve the above problems, there is a problem in that leakage current is generated due to plasma damage by sputter etching, thereby degrading isolation characteristics of the device.
    The present invention has been made to solve the above problems of the device isolation layer forming method of the prior art, and improves the isolation characteristics of the device by filling the trench by continuously depositing the APCVD oxide layer and the HDPCVD oxide layer in the STI process. It is an object of the present invention to provide a method for forming a device isolation layer of a semiconductor device that is suitable for use.
    1A and 1B are process cross-sectional views of a device isolation layer of the prior art.
    2A and 2B are process cross-sectional views of another device isolation layer of the prior art.
    3A-3D are cross sectional views of a device isolation layer in accordance with the present invention.
    Explanation of symbols for main parts of the drawings
    30. Semiconductor substrate 31. Thermal oxide layer
    32. Nitride layer 33. APCVD oxide layer
    34. HDPCVD oxide layer
    The method of forming a device isolation layer of a semiconductor device of the present invention for improving device isolation characteristics of a semiconductor device includes forming a thermal oxide layer on a surface of a semiconductor substrate including an active region and a device isolation region that isolates the region. Forming a nitride layer on the oxide layer, selectively etching the nitride layer and patterning the nitride layer so as to remain only in the region except the device isolation region, and selectively etching the thermal oxide layer and the semiconductor substrate using the mask as a mask to form a trench of a predetermined depth; Forming the APCVD oxide layer on the entire surface of the trench, forming the oxide layer on the trench surface, and forming the APCVD oxide layer on the entire surface including the thermal oxide layer and the patterned nitride layer; and the entire surface of the APCVD oxide layer. Forming and heat-treating the HDPCVD oxide layer thereon; and polishing the HDPCVD oxide layer by the CMP process. Including the step of the trench to leave only part it characterized in that formed.
    Hereinafter, a device isolation layer forming method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
    3A-3D are cross-sectional views of a device isolation layer in accordance with the present invention.
    In the method of forming a device isolation layer of the semiconductor device of the present invention, first, as shown in FIG. 3A, a thermal oxide layer is formed on a surface of a semiconductor substrate 30 including an active region in which actual cells are formed and a device isolation region separating the region. (31) is formed, and the nitride film layer 32 is formed on the thermal oxide layer 31 by the LPCVD process.
    As shown in FIG. 3B, the nitride layer 32 is selectively etched and patterned so as to remain only in portions except the device isolation region. Subsequently, the thermal oxide layer 31 and the semiconductor substrate 30 are selectively etched using the patterned nitride layer 32 as a mask to form trenches having a predetermined depth. At this time, the trench forming process is a etch (Reactive Ion Etching) process to etch the wall surface of the trench to have an inclination of 80 ~ 88 °.
    Subsequently, a thermal oxidation film layer having a thickness of 50 to 100 kPa is formed again on the surface of the trench by a thermal oxidation process. An APCVD oxide layer 33 (or LPCVD oxide layer) is formed on the entire surface including the re-formed thermal oxide layer and the patterned nitride layer 32.
    At this time, the APCVD oxide layer 33 (or LPCVD oxide layer) is formed of an oxide film doped with impurities and has a thickness of 200 to 500 kPa.
    Subsequently, as shown in FIG. 3C, the HDPCVD oxide layer 34 is formed on the entire surface of the APCVD oxide layer 33 to a thickness of about 5000 to 8000 Pa. And in the N 2 gas atmosphere to carry out heat treatment of 900 ~ 1000 ℃. In this case, the HDPCVD oxide layer 34 uses an oxide layer doped with impurities, and the HDP source includes an ICP (Inductively Coupled Plasma), a Helicon Plasma, or an ECR (Electron Cyclotron Resonance). In the formation process of the oxide film 34, the deposition ratio / sputter ratio is set to 2.9 to 3.9.
    As shown in FIG. 3D, the HDPCVD oxide layer 34 is polished by a chemical mechanical polishing (CMP) process to form a device isolation layer embedded only in the trench portion.
    The device isolation layer forming process of the semiconductor device of the present invention uses an APCVD oxide layer (or LPCVD oxide layer) as a buffer layer to improve device isolation characteristics, and the HDPCVD oxide layer having good buried characteristics even in a wide device isolation region ( 34) to form a device isolation layer.
    The device isolation layer forming method of the semiconductor device of the present invention uses the APCVD (or LPCVD) oxide layer as the buffer layer when forming the device isolation layer of the STI structure, thereby reducing the occurrence of leakage current and improving device isolation characteristics. .
    In addition, since the trench is filled using a HDPCVD oxide film having good embedding characteristics in a wide area, it is possible to reduce the occurrence of defects such as dishing, thereby improving device isolation characteristics.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] Forming a thermal oxide layer on the surface of the semiconductor substrate including an active region and an element isolation region that isolates the region, and forming a nitride layer on the thermal oxide layer;
    Selectively etching the nitride film layer so as to remain only in portions except the device isolation region, and selectively etching the thermal oxide layer and the semiconductor substrate using the mask as a mask to form a trench having a predetermined depth;
    Re-forming a thermal oxide layer on the trench surface and forming an APCVD oxide layer on the entire surface including the thermal oxide layer and the patterned nitride layer;
    Forming and heat-treating an HDPCVD oxide layer on the entire surface of the APCVD oxide layer;
    And polishing the above HDPCVD oxide layer by a CMP process so that only the trench portion remains.
    [2" claim-type="Currently amended] The method of claim 1, wherein the trench is formed by a reactive ion etching (RIE) process such that a wall surface of the trench has an inclination of 80 ° to 88 °.
    [3" claim-type="Currently amended] Selectively etching the semiconductor substrate to form a trench;
    Forming an APCVD oxide film on the trench;
    Forming a HDPCVD oxide film on the APCVD oxide film to fill the trench.
    [4" claim-type="Currently amended] 4. The semiconductor device according to claim 3, wherein the HDPCVD oxide layer is formed of an oxide layer doped with impurities and has a thickness of about 5000 to 8000 Pa. The heat treatment process conditions are performed at 900 to 1000 DEG C in an N 2 gas atmosphere. Device isolation layer formation method of the.
    [5" claim-type="Currently amended] Selectively etching the semiconductor substrate to form a trench;
    Forming an APCVD oxide film on the trench;
    Forming a HDPCVD oxide film on the APCVD oxide film to fill the trench.
    [6" claim-type="Currently amended] 6. The semiconductor device according to claim 5, wherein the HDPCVD oxide layer is formed of an oxide film doped with impurities and has a thickness of about 5000 to 8000 Pa, and the heat treatment process conditions are performed at 900 to 1000 DEG C in an N 2 gas atmosphere. Device isolation layer formation method of the.
    类似技术:
    公开号 | 公开日 | 专利标题
    US5989978A|1999-11-23|Shallow trench isolation of MOSFETS with reduced corner parasitic currents
    US5455194A|1995-10-03|Encapsulation method for localized oxidation of silicon with trench isolation
    US5313094A|1994-05-17|Thermal dissipation of integrated circuits using diamond paths
    KR100253079B1|2000-04-15|Semiconductor element trench isolation method
    US6576558B1|2003-06-10|High aspect ratio shallow trench using silicon implanted oxide
    KR100322531B1|2002-03-18|Method for Trench Isolation using a Dent free layer &Semiconductor Device thereof
    KR100428806B1|2004-04-28|Structure of Trench Isolation and Method of Forming The Same
    US6583025B2|2003-06-24|Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace
    DE10127622B4|2009-10-22|Method of making an isolation trench filled with HDPCVD oxide
    KR100230431B1|1999-11-15|Method of forming trench isolation using two kinds of oxides films
    KR100421046B1|2004-03-04|Semiconductor device and method for manufacturing the same
    TW396520B|2000-07-01|Process for shallow trench isolation
    TWI253114B|2006-04-11|Semiconductor device with trench isolation structure and method for fabricating the same
    KR100543455B1|2006-01-23|Method for forming trench isolation in semiconductor device
    KR100428805B1|2004-04-28|Structure of Trench Isolation and Method of Forming The Same
    KR20040099533A|2004-12-02|Method of fabricating recess transistor in integrated circuit device recess transistor and recess transistor in integrated circuit device fabricated by the same
    US6180493B1|2001-01-30|Method for forming shallow trench isolation region
    US5885883A|1999-03-23|Methods of forming trench-based isolation regions with reduced susceptibility to edge defects
    KR100312943B1|2001-11-03|A semiconductor device and fabricating method thereof
    US6583488B1|2003-06-24|Low density, tensile stress reducing material for STI trench fill
    US6602792B2|2003-08-05|Method for reducing stress of sidewall oxide layer of shallow trench isolation
    KR100249025B1|2000-03-15|Semiconductor element isolating method
    US6777336B2|2004-08-17|Method of forming a shallow trench isolation structure
    US20030003678A1|2003-01-02|Method of forming shallow trench isolation for thin silicon-on-insulator substrates
    FR2826179A1|2002-12-20|Deep insulating trench in a semiconductor substrate with side walls and base covered with an insulating material defining an empty cavity and forming a plug to seal this cavity
    同族专利:
    公开号 | 公开日
    US6033970A|2000-03-07|
    KR100239453B1|2000-01-15|
    JP2957169B2|1999-10-04|
    JPH11163120A|1999-06-18|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-11-06|Application filed by 구본준, 엘지반도체 주식회사
    1997-11-06|Priority to KR1019970058531A
    1999-06-05|Publication of KR19990038702A
    2000-01-15|Application granted
    2000-01-15|Publication of KR100239453B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970058531A|KR100239453B1|1997-11-06|1997-11-06|Method of forming a device isolation film of semiconductor device|
    [返回顶部]